Ultra-low-power (ULP) short-range wireless connectivity is becoming increasingly relevant to a wide range of sensor and actuator node applications ranging from consumer life style to medical applications. In recent years a multitude of wireless standards has been proposed to meet differing requirements of individual application domains such as data rates, range, Quality-of-Service (QoS), and peak and average power consumption. From a commercial perspective, a single radio component supporting multiple wireless standards—targeting at multiple application domains/markets—while reducing integration costs is preferable. In particular for mobile applications, reduction of radio power consumption and hence also synchronization hardware power consumption is of importance to allow for small device form factors and long operating times. At the same time, various wireless standards, utilizing different modulation schemes, have to be supported by a single radio architecture which may not compromise low power operation or suitable silicon area.
An important part of establishing and maintaining a wireless communication link between two radio transceivers is the timing synchronization of the receiver with the transmitter system. A general problem of timing synchronization in wireless systems is to find near-optimum sampling instants of baseband signals. Typically, receivers are sampling the baseband signal at a rate higher than the baseband symbol transmission rate, employing a certain oversampling ratio N, yielding a number of N samples representing each baseband symbol. The timing synchronization unit serves the purpose of determining near-optimum sampling timing instants of the oversampled baseband signals for given baseband symbols.
The present disclosure is specifically concerned with circuits for timing synchronization, which form an important aspect in the design of a communication system.
FIG. 1 illustrates the principle of the symbol timing synchronization based on a timing error function for an arbitrary baseband signal. For the given example, the optimum sampling instants are represented by the positive and negative peak values as well as by the zero-crossing instant (shown with arrows) of given baseband signal. In an aligned sampling case, e.g., the actual sampling instant is aligned with the desired sampling instants, for example, represented by the peak value of the illustrated triangular signal. In this case, a timing error function evaluating the sampling alignment outputs a near-zero value indicating little or no timing error. In the non-aligned sampling cases, e.g., when the sampling instant is too early or too late, the timing error function outputs a large magnitude with a negative or positive sign depending on whether the baseband signal was sampled early or late with respect to the desired sampling instants.
The task of finding the optimal baseband symbol sampling instant typically comprises the following subparts:
a) detecting a timing offset,
b) determining how to adjust the timing, and
c) actually compensating for the timing offset.
For digital radio receivers, different circuits have been proposed for subtask a), such as circuits based on Gardner, early-late gate, Muller & Muller, correlation algorithms, etc. For subtask b), typically loop filters based on PID controllers or similar schemes are employed. For subtask c), compensation in the digital domain (interpolation filters) or feedback to control the ADC clock have been proposed. Many proposed solutions are tailored to a particular modulation scheme/wireless standard and lack the flexibility to operate on different modulation schemes.
Techniques for determining the optimal baseband symbol sampling instant have been well studied in the art. Conventional solutions, however, are tailored to a particular modulation scheme or a wireless standard and lack flexibility to operate on different modulation schemes. Furthermore, they are typically only used for timing acquisition in the preamble section of the wireless data packet, while for timing tracking another circuit is required as the data payload is unknown. In addition they contain high complexity modules such as correlators, interpolators and decimation filters, and the like. This increases the computational as well as the circuit complexity, and may lead to higher power consumption and larger silicon area.
Traditionally, correlation-based approaches are frequently used for timing acquisition between transmitter (TX) and receiver (RX) systems. However, correlation-based approaches are typically only employed for initial timing acquisition, not for timing tracking during frame reception, because of the higher costs in terms of power consumption (needs to be continuously active during the whole frame). Furthermore, these approaches rely on the occurrence of correlation patterns which is typically only the case for the preamble of a frame but not for the payload part (abbreviated as PSDU). Hence, they will generally only work for a predefined pattern over multiple symbols during preamble reception (where the expected sequence of symbols is known) but for timing correction during PSDU reception (timing tracking), where the incoming symbol sequence is not known on the receiver side, another approach should be used. Besides, they are typically operating on higher-rate oversampled data (e.g., 8 samples per symbol).
Conventionally, the Gardner algorithm is used for timing tracking in a PSK type of system after the acquisition. It only requires 2 samples per symbol and hence the processing rate or clock speed can be lower. Note that timing tracking is also important because timing drifts during the packet. Without timing tracking, the optimal sampling point will drift away.
As already mentioned, several problems can be identified concerning current solutions for baseband symbol timing synchronization. One has to deal with a multitude of wireless standards (e.g., for personal area networks (PANs)) based on different modulation schemes with different symbol timing synchronization requirements that needs to be supported by a single architecture. Current approaches offer limited flexibility (e.g., single standard support), hence a multitude of timing synchronization circuits is required to support different wireless standards. Another problem relates to the high complexity of the applied timing synchronization algorithms. Further, different circuits are needed for performing initial timing synchronization and timing tracking, which additionally contributes to higher complexity, higher power and area consumption.
To demonstrate the different requirements for initial timing synchronization for different modulation schemes, a brief recapitulation of some basic information on the latter is now provided.
Frequency-shift keying (FSK) is a frequency modulation scheme in which information is carried via discrete frequency changes. The modulated signal is discontinuous at the symbol switching time. Therefore, it is also called discontinuous-phase FSK. The sharp phase transitions result in relatively prominent side-lobe levels of the signal spectrum compared to the main lobe, which means the signal should be transmitted in a wider frequency band, otherwise it ends up with increased interference levels in the adjacent channels.
In order to solve this problem, Continuous Phase Frequency Shift Keying (CPFSK) was introduced. The phase continuity yields high spectral efficiency and the constant envelope yields excellent power efficiency. CPFSK belongs to the big family of Continuous Phase Modulation (CPM). A CPM modulated signal can be expressed as
                              s          ⁡                      (            t            )                          =                                                            2                ⁢                ℰ                            T                                ⁢                      cos            ⁡                          [                                                2                  ⁢                  π                  ⁢                                                                          ⁢                                      f                    c                                                  +                                  ϕ                  ⁡                                      (                                          t                      ;                      I                                        )                                                  +                                  ϕ                  0                                            ]                                                          (        1        )            where Φ0 is the initial phase of the carrier and φ(t; I) is given as
                                          ϕ            ⁡                          (                              t                ;                I                            )                                =                      2            ⁢            π            ⁢                                          ∑                                  k                  =                                      -                    ∞                                                  n                            ⁢                                                I                  k                                ⁢                                  h                  k                                ⁢                                  q                  ⁡                                      (                                          t                      -                      kT                                        )                                                                                      ,                  nT          ≤          t          ≤                                    (                              n                +                1                            )                        ⁢            T                                              (        2        )            here {Ik} is the sequence of M-ary information symbols selected from the alphabet ±1, ±3, . . . , ±(M−1), {hk} is a sequence of modulation indices and q(t) is the normalized waveform shape. If hk=h for all k, the modulation index is fixed for all symbols and is given ash=2fdT  (3)In equation (3) fd is the peak frequency deviation and T is the symbol duration in seconds. The waveform q(t) may be represented, without a loss of generality, as the integral of some pulse shape g(t), i.e.,q(t)=∫−∞tg(τ)dτ  (4)If g(t)=0, t>T, the CPM signal is called full response, otherwise the modulated signal is referred to as partial response CPM.
In CPM each symbol is modulated by gradually changing the phase of the carrier from the starting value to the final value, over the symbol duration. The modulation and demodulation becomes more complex given the fact that the initial phase of each symbol is determined by the cumulative total phase of all previous transmitted symbols, which is known as the phase memory. Therefore, the receiver cannot make decisions on any isolated symbol without taking the previous symbols into account.
Minimum Shift Keying (MSK) modulation is a special subclass of CPFSK modulation with a frequency separation of one-half the bit rate, or one says the modulation index h=½. Offset Quadrature Phase-shift Keying (OQPSK) is a variant of QPSK. It is sometimes called Staggered QPSK (SQPSK). In QPSK two bits can change at the same time to jump from one symbol to another, and hence it allows the phase of the signal to jump by as much as 180° at a time. When the signal is low-pass filtered (as is typical in a transmitter), these phase shifts result in large amplitude fluctuations. By offsetting the timing of the odd and even bits by one bit-period, or half a symbol period, it is assured that the in-phase and quadrature components do not change at the same moment. This means the phase-shift in the constellation will not be more than 90° at a time. This yields much lower amplitude fluctuations than non-offset QPSK. By applying half-sine pulse shaping to OQPSK, it is equivalent to MSK.
Different from the original MSK or FSK, in a GMSK or GFSK transmitter, the digital data stream is shaped with a Gaussian filter before being applied to a frequency modulator. The advantage is in reduced sideband power, which in turn reduces interference in adjacent frequency channels. However, the drawback is that the Gaussian filter increases the modulation memory in the system and causes inter-symbol interference. The Gaussian filter is specified by bandwidth symbol time product BTb. For smaller values of BTb, the spectral side-lobes are reduced further, but the inter-symbol interference (ISI) increases.
The optimum GFSK demodulator is a trellis-based Viterbi decoder, where it always assumes a certain nominal value for the modulation index h. However, the modulation index in Bluetooth Low Energy systems, for example, is allowed to vary within the range of 0.45-0.55, which leads to a varying trellis structure for sequence detection with possibly a large number of states. Therefore, in low power design, non-coherent suboptimal receivers are typically used to demodulate GFSK signals. As indicated by equation (2), in one symbol period the phase trellis of a GFSK signal is piece-wise monotonic. The direction of the monotonic change is determined by the binary symbol value. Hence, a differential demodulator can be employed. A differential demodulator involves sampling φ(t) at symbol rate to obtain φ(nT) and then taking the difference of the neighbouring samplesΔφ(nT)=φ(nT)−φ(nT−T)  (5)A decision can be made based on the sign of Δφ(nT). The same differential detector can be applied to MSK and CPFSK as well.
In differentially encoded BPSK a binary ‘1’ may be transmitted by adding 180° to the current phase and a binary ‘0’ by adding 0° to the current phase. Another variant of DPSK is Symmetric Differential Phase Shift keying, SDPSK, where encoding would be +90° for a ‘1’ and −90° for a ‘0’. It is obvious a differential demodulator applies well to a DPSK/SDPSK system, where the demodulator determines the changes in the phase of the received signal rather than the absolute phase itself.
In U.S. Pat. No. 8,249,198 a demodulation circuit is disclosed for differential phase shift keying (DPSK) modulated signals. A phase difference data generator compares phase data representing a phase of the received signal input at every predetermined sampling time with previous phase data preceding by one symbol time to generate phase difference data representing a phase shift amount of the phase data. A symbol selection unit evaluates the phase difference data generated at every sampling time to select as a symbol. In other words, a symbol phase based approach is adopted. The proposed solution involves a high computational complexity and is vulnerable to frequency offset.
The paper “Synchronization Scheme in Non-Coherent Demodulator for TDMA Digital Mobile Radio System” (Liu et al, Proc. Int'l Symposium on Circuits and Systems, ISCAS1999, vol. 4, pp. 463-466, 1999) presents a synchronization scheme in a non-coherent demodulator for a TDMA digital mobile radio system. The proposed synchronization scheme is combined with non-linear symbol timing recovery using Gardner's timing error detector and also deals with frequency offset compensation. A differential detector is used with a fixed delay for demodulating input IQ data before performing timing error detection. This approach, however, is limited to a specific baseband modulation scheme and/or symbol rate, i.e. DQPSK. Furthermore, the output of the differential detector, and hence, the subsequent timing error detector is affected by the input signal amplitude. Another limitation is that the carrier frequency offset compensation is applied to the signal after the timing error estimation. Therefore, for large frequency offsets, e.g., as defined in the Bluetooth Low Energy standard, the timing error estimator as described cannot function. Furthermore, the proposed solution directly modifies the sampling process of the ADC in the analog domain, which adds complexity to the ADC design and leads to phase distortion and slower timing loop settling time of the timing compensation.
Hence, there is a need for a timing synchronization circuit wherein one or more of these drawbacks are avoided or overcome.